forked from github/verilator
8 lines
577 B
Plaintext
8 lines
577 B
Plaintext
%Warning-WIDTH: t/t_flag_context_bad.v:9:19: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's CONST '5'h1f' generates 5 bits.
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: ... In instance t
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... For warning description see https://verilator.org/warn/WIDTH?v=latest
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... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
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%Warning-UNUSEDSIGNAL: t/t_flag_context_bad.v:9:15: Signal is not used: 'foo'
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: ... In instance t
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%Error: Exiting due to
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