forked from github/verilator
20 lines
414 B
Systemverilog
20 lines
414 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for Issue#2863
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2021 by Julien Margetts (Originally provided by Thomas Sailer)
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module test
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(input logic [1:0] a,
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input logic e,
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output logic [1:0] z);
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always_latch
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if (e)
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z[0] <= a[0];
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always_latch
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if (e)
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z[1] <= a[1];
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endmodule
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