forked from github/verilator
32 lines
1.7 KiB
Plaintext
32 lines
1.7 KiB
Plaintext
%Warning-ASSIGNDLY: t/t_delay.v:22:13: Unsupported: Ignoring timing control on this assignment.
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: ... In instance t
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22 | assign #(1.2000000000000000) dly1 = dly0 + 32'h1;
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| ^~~~~~~~~~~~~~~~~~
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... For warning description see https://verilator.org/warn/ASSIGNDLY?v=latest
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... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message.
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%Warning-ASSIGNDLY: t/t_delay.v:27:19: Unsupported: Ignoring timing control on this assignment.
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: ... In instance t
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27 | dly0 <= #0 32'h11;
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| ^
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%Warning-ASSIGNDLY: t/t_delay.v:30:19: Unsupported: Ignoring timing control on this assignment.
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: ... In instance t
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30 | dly0 <= #0.12 dly0 + 32'h12;
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| ^~~~
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%Warning-ASSIGNDLY: t/t_delay.v:38:26: Unsupported: Ignoring timing control on this assignment.
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: ... In instance t
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38 | dly0 <= #(dly_s.dly) 32'h55;
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| ^~~
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%Warning-STMTDLY: t/t_delay.v:43:11: Unsupported: Ignoring delay on this delayed statement.
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: ... In instance t
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43 | #100 $finish;
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| ^~~
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%Warning-UNUSED: t/t_delay.v:20:12: Signal is not used: 'dly_s'
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: ... In instance t
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20 | dly_s_t dly_s;
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| ^~~~~
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%Warning-BLKSEQ: t/t_delay.v:37:20: Blocking assignment '=' in sequential logic process
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: ... Suggest using delayed assignment '<='
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37 | dly_s.dly = 55;
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| ^
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%Error: Exiting due to
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