forked from github/verilator
49 lines
1.1 KiB
Verilog
49 lines
1.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2010 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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in
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);
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input in; // inputs don't get flagged as undriven
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output out; // outputs don't get flagged as unused
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wire out = in;
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sub sub ();
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endmodule
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module sub;
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wire pub /*verilator public*/; // Ignore publics
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wire [5:0] assunu1 = 0; // Assigned but unused
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wire [3:0] assunub2 = 0; // Assigned but bit 2 unused
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wire [15:10] udrb2; // [14:13,11] is undriven
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assign udrb2[15] = 0;
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assign udrb2[12] = 0;
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assign udrb2[10] = 0;
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wire unu3; // Totally unused
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wire [3:0] mixed; // [3] unused & undr, [2] unused, [1] undr, [0] ok
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assign mixed[2] = 0;
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assign mixed[0] = 0;
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localparam THREE = 3;
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initial begin
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if (0 && assunu1[0] != 0 && udrb2 != 0) begin end
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if (0 && assunub2[THREE] && assunub2[1:0]!=0) begin end
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if (0 && mixed[1:0] != 0) begin end
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end
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endmodule
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