verilator/test_regress
Yutetsu TAKATSUKASA f3b10df454
Skip merging assign statements if a variable is marked split_var to fix #3177 (#3179)
* add tests to reproduce #3177.

Any random test circuits can be added to t_split_var_4.v later because it uses CRC to check the result while
t_split_var_0.v has just barrel shifters.

* Fix #3177. Don't merge assign statements if a variable is marked split_var.
2021-10-25 20:56:59 +09:00
..
t Skip merging assign statements if a variable is marked split_var to fix #3177 (#3179) 2021-10-25 20:56:59 +09:00
.gdbinit
.gitignore
CMakeLists.txt
driver.pl Internal coverage: Fix some test runs having conflicting sources. 2021-10-05 20:22:29 -04:00
input.vc
input.xsim.vc
Makefile
Makefile_obj