forked from github/verilator
39 lines
738 B
Systemverilog
39 lines
738 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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int value;
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initial begin
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wait (value == 1);
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if (value != 1) $stop;
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wait (0);
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if (value != 1) $stop;
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//
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wait (value == 2);
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if (value != 2) $stop;
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//
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wait (value == 3) if (value != 3) $stop;
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if (value != 3) $stop;
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end
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initial begin
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#10;
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value = 1;
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#10;
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value = 2;
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#10;
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value = 3;
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#10;
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value = 4;
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#10;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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