forked from github/verilator
33 lines
855 B
Perl
Executable File
33 lines
855 B
Perl
Executable File
#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2022 by Antmicro Ltd. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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if (!$Self->have_coroutines) {
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skip("No coroutine support");
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}
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else {
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top_filename("t/t_timing_clkgen1.v");
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compile(
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verilator_flags2 => ["--timing --trace -Wno-MINTYPMAXDLY"],
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timing_loop => 1
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);
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execute(
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check_finished => 1,
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);
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vcd_identical($Self->trace_filename, $Self->{golden_filename});
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}
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ok(1);
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1;
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