forked from github/verilator
1816 lines
100 KiB
XML
1816 lines
100 KiB
XML
<?xml version="1.0" ?>
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<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
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<verilator_xml>
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<files>
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<file id="a" filename="<built-in>" language="1800-2017"/>
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<file id="b" filename="<command-line>" language="1800-2017"/>
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<file id="c" filename="input.vc" language="1800-2017"/>
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<file id="d" filename="t/t_enum_type_methods.v" language="1800-2017"/>
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</files>
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<module_files>
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<file id="d" filename="t/t_enum_type_methods.v" language="1800-2017"/>
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|
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</begin>
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|
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|
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<cfunc loc="a,0,0,0,0" name="_eval_settle"/>
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|
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|
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|
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|
</textblock>
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|
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|
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|
<ccast loc="d,10,8,10,9" dtype_id="9">
|
|
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|
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|
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|
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<ccall loc="a,0,0,0,0" dtype_id="7" func="_eval_nba"/>
|
|
</stmtexpr>
|
|
</begin>
|
|
</if>
|
|
</begin>
|
|
</while>
|
|
</cfunc>
|
|
<cfunc loc="d,10,8,10,9" name="_eval_debug_assertions">
|
|
<if loc="d,14,10,14,13">
|
|
<and loc="d,14,10,14,13" dtype_id="1">
|
|
<varref loc="d,14,10,14,13" name="clk" dtype_id="1"/>
|
|
<const loc="d,14,10,14,13" name="8'hfe" dtype_id="17"/>
|
|
</and>
|
|
<begin>
|
|
<cstmt loc="d,14,10,14,13">
|
|
<text loc="d,14,10,14,13"/>
|
|
</cstmt>
|
|
</begin>
|
|
</if>
|
|
</cfunc>
|
|
<cfunc loc="d,10,8,10,9" name="_ctor_var_reset">
|
|
<creset loc="d,14,10,14,13">
|
|
<varref loc="d,14,10,14,13" name="clk" dtype_id="1"/>
|
|
</creset>
|
|
<creset loc="d,22,17,22,20">
|
|
<varref loc="d,22,17,22,20" name="t.cyc" dtype_id="4"/>
|
|
</creset>
|
|
<creset loc="d,23,9,23,10">
|
|
<varref loc="d,23,9,23,10" name="t.e" dtype_id="2"/>
|
|
</creset>
|
|
<creset loc="d,10,8,10,9">
|
|
<varref loc="d,10,8,10,9" name="__Vtrigrprev__TOP__clk" dtype_id="1"/>
|
|
</creset>
|
|
</cfunc>
|
|
<cuse loc="a,0,0,0,0" name="$unit"/>
|
|
</module>
|
|
<package loc="a,0,0,0,0" name="$unit" origName="__024unit">
|
|
<var loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12" vartype="" origName="__Venumtab_enum_next0">
|
|
<initarray>
|
|
<inititem index="1">
|
|
<const loc="d,18,30,18,31" name="4'h3" dtype_id="11"/>
|
|
</inititem>
|
|
<inititem index="3">
|
|
<const loc="d,19,30,19,31" name="4'h4" dtype_id="11"/>
|
|
</inititem>
|
|
<inititem index="4">
|
|
<const loc="d,17,30,17,31" name="4'h1" dtype_id="11"/>
|
|
</inititem>
|
|
</initarray>
|
|
</var>
|
|
<var loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15" vartype="" origName="__Venumtab_enum_prev1">
|
|
<initarray>
|
|
<inititem index="1">
|
|
<const loc="d,19,30,19,31" name="4'h4" dtype_id="11"/>
|
|
</inititem>
|
|
<inititem index="3">
|
|
<const loc="d,17,30,17,31" name="4'h1" dtype_id="11"/>
|
|
</inititem>
|
|
<inititem index="4">
|
|
<const loc="d,18,30,18,31" name="4'h3" dtype_id="11"/>
|
|
</inititem>
|
|
</initarray>
|
|
</var>
|
|
<var loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="16" vartype="" origName="__Venumtab_enum_name2">
|
|
<initarray>
|
|
<inititem index="1">
|
|
<const loc="d,16,12,16,16" name=""E01"" dtype_id="10"/>
|
|
</inititem>
|
|
<inititem index="3">
|
|
<const loc="d,16,12,16,16" name=""E03"" dtype_id="10"/>
|
|
</inititem>
|
|
<inititem index="4">
|
|
<const loc="d,16,12,16,16" name=""E04"" dtype_id="10"/>
|
|
</inititem>
|
|
</initarray>
|
|
</var>
|
|
<scope loc="a,0,0,0,0" name="$unit"/>
|
|
<cfunc loc="a,0,0,0,0" name="_ctor_var_reset">
|
|
<creset loc="d,16,12,16,16">
|
|
<varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
|
|
</creset>
|
|
<creset loc="d,16,12,16,16">
|
|
<varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
|
|
</creset>
|
|
<creset loc="d,16,12,16,16">
|
|
<varref loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="16"/>
|
|
</creset>
|
|
</cfunc>
|
|
</package>
|
|
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck__Syms.cpp"/>
|
|
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck__Syms.h"/>
|
|
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck.h"/>
|
|
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck.cpp"/>
|
|
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck_$root.h"/>
|
|
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck_$unit.h"/>
|
|
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck_$root__Slow.cpp"/>
|
|
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck_$root__DepSet_h########__0__Slow.cpp"/>
|
|
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck_$root__DepSet_h########__0__Slow.cpp"/>
|
|
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck_$root__DepSet_h########__0.cpp"/>
|
|
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck_$root__DepSet_h########__0.cpp"/>
|
|
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck_$unit__Slow.cpp"/>
|
|
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck_$unit__DepSet_h########__0__Slow.cpp"/>
|
|
<typetable loc="a,0,0,0,0">
|
|
<basicdtype loc="d,32,24,32,27" id="1" name="logic"/>
|
|
<basicdtype loc="d,52,16,52,17" id="14" name="logic" left="31" right="0"/>
|
|
<basicdtype loc="d,16,17,16,18" id="2" name="logic" left="3" right="0"/>
|
|
<enumdtype loc="d,16,12,16,16" id="18" name="t.my_t" sub_dtype_id="2">
|
|
<enumitem loc="d,17,24,17,27" name="E01" dtype_id="11">
|
|
<const loc="d,17,30,17,31" name="4'h1" dtype_id="11"/>
|
|
</enumitem>
|
|
<enumitem loc="d,18,24,18,27" name="E03" dtype_id="11">
|
|
<const loc="d,18,30,18,31" name="4'h3" dtype_id="11"/>
|
|
</enumitem>
|
|
<enumitem loc="d,19,24,19,27" name="E04" dtype_id="11">
|
|
<const loc="d,19,30,19,31" name="4'h4" dtype_id="11"/>
|
|
</enumitem>
|
|
</enumdtype>
|
|
<basicdtype loc="d,22,4,22,11" id="4" name="integer" left="31" right="0" signed="true"/>
|
|
<refdtype loc="d,23,4,23,8" id="19" name="my_t" sub_dtype_id="2"/>
|
|
<basicdtype loc="d,27,4,27,10" id="10" name="string"/>
|
|
<unpackarraydtype loc="d,16,12,16,16" id="12" sub_dtype_id="2">
|
|
<range loc="d,16,12,16,16">
|
|
<const loc="d,16,12,16,16" name="32'h7" dtype_id="14"/>
|
|
<const loc="d,16,12,16,16" name="32'h0" dtype_id="14"/>
|
|
</range>
|
|
</unpackarraydtype>
|
|
<unpackarraydtype loc="d,16,12,16,16" id="15" sub_dtype_id="2">
|
|
<range loc="d,16,12,16,16">
|
|
<const loc="d,16,12,16,16" name="32'h7" dtype_id="14"/>
|
|
<const loc="d,16,12,16,16" name="32'h0" dtype_id="14"/>
|
|
</range>
|
|
</unpackarraydtype>
|
|
<unpackarraydtype loc="d,16,12,16,16" id="16" sub_dtype_id="10">
|
|
<range loc="d,16,12,16,16">
|
|
<const loc="d,16,12,16,16" name="32'h7" dtype_id="14"/>
|
|
<const loc="d,16,12,16,16" name="32'h0" dtype_id="14"/>
|
|
</range>
|
|
</unpackarraydtype>
|
|
<refdtype loc="d,51,12,51,16" id="20" name="my_t" sub_dtype_id="2"/>
|
|
<basicdtype loc="d,22,23,22,24" id="8" name="logic" left="31" right="0" signed="true"/>
|
|
<voiddtype loc="d,10,8,10,9" id="7"/>
|
|
<basicdtype loc="d,10,8,10,9" id="6" name="VlTriggerVec"/>
|
|
<basicdtype loc="d,10,8,10,9" id="5" name="bit" left="31" right="0"/>
|
|
<basicdtype loc="d,10,8,10,9" id="3" name="bit"/>
|
|
<basicdtype loc="d,60,22,60,25" id="9" name="logic" left="31" right="0"/>
|
|
<basicdtype loc="d,31,11,31,14" id="11" name="logic" left="31" right="0"/>
|
|
<basicdtype loc="d,37,17,37,21" id="13" name="logic" left="31" right="0"/>
|
|
<basicdtype loc="d,14,10,14,13" id="17" name="logic" left="7" right="0"/>
|
|
</typetable>
|
|
<constpool>
|
|
<module loc="a,0,0,0,0" name="@CONST-POOL@" origName="@CONST-POOL@">
|
|
<scope loc="a,0,0,0,0" name="TOP"/>
|
|
</module>
|
|
</constpool>
|
|
</netlist>
|
|
</verilator_xml>
|