forked from github/verilator
126 lines
2.3 KiB
Systemverilog
126 lines
2.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2010 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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`ifndef IVERILOG
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import "DPI-C" context function int mon_check();
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`endif
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package somepackage;
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int someint /*verilator public_flat_rw*/;
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endpackage
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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`ifdef USE_DOLLAR_C32
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`systemc_header
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extern "C" int mon_check();
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`verilog
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`endif
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input clk;
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integer status;
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wire a, b, x;
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A \mod.a (/*AUTOINST*/
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// Outputs
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.x (x),
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// Inputs
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.clk (clk),
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.a (a),
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.b (b));
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// Test loop
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initial begin
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`ifdef IVERILOG
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status = $mon_check();
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`elsif USE_DOLLAR_C32
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status = $c32("mon_check()");
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`else
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status = mon_check();
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`endif
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if (status!=0) begin
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$write("%%Error: t_vpi_module.cpp:%0d: C Test failed\n", status);
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$stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule : t
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module A(/*AUTOARG*/
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// Outputs
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x,
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// Inputs
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clk, a, b
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);
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input clk;
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input a, b;
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output x;
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wire y, c;
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B \mod_b$ (/*AUTOINST*/
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// Outputs
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.y (y),
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// Inputs
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.b (b),
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.c (c));
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C \mod\c$ (/*AUTOINST*/
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// Outputs
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.x (x),
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// Inputs
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.clk (clk),
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.a (a),
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.y (y));
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endmodule : A
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module B(/*AUTOARG*/
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// Outputs
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y,
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// Inputs
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b, c
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); /*verilator public_module*/
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input b, c;
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output reg y;
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always @(*) begin : myproc
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y = b ^ c;
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end
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endmodule
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module C(/*AUTOARG*/
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// Outputs
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x,
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// Inputs
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clk, a, y
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);
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input clk;
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input a, y;
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output reg x /* verilator public_flat_rw */;
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always @(posedge clk) begin
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x <= a & y;
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end
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endmodule
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