forked from github/verilator
92 lines
2.3 KiB
Systemverilog
92 lines
2.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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reg [63:0] crc;
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reg [255:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [127:0] in = {~crc[63:0], crc[63:0]};
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [127:0] o1; // From test of Test.v
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wire [127:0] o2; // From test of Test.v
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// End of automatics
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Test test (/*AUTOINST*/
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// Outputs
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.o1 (o1[127:0]),
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.o2 (o2[127:0]),
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// Inputs
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.in (in[127:0]));
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x %x\n", $time, cyc, crc, o1, o2);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= {o1,o2} ^ {sum[254:0],sum[255]^sum[2]^sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= '0;
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end
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else if (cyc<10) begin
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sum <= '0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 256'h008a080aaa000000140550404115dc7b008a080aaae7c8cd897bc1ca49c9350a
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test (/*AUTOARG*/
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// Outputs
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o1, o2,
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// Inputs
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in
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);
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input [127:0] in;
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output logic [127:0] o1;
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output logic [127:0] o2;
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always_comb begin: b_test
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logic [127:0] tmpp;
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logic [127:0] tmp;
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tmp = '0;
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tmpp = '0;
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tmp[63:0] = in[63:0];
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tmpp[63:0] = in[63:0];
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tmpp[63:0] = {tmp[0+:32], tmp[32+:32]};
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tmp[63:0] = {tmp[0+:32], tmp[32+:32]};
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o1 = tmp;
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o2 = tmpp;
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end
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endmodule
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