forked from github/verilator
31 lines
592 B
Systemverilog
31 lines
592 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2004 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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//bug830
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module sub();
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endmodule
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function integer cdiv(input integer x);
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begin
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cdiv = 10;
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end
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endfunction
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module t (/*AUTOARG*/);
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genvar j;
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generate
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for (j = 0; j < cdiv(10); j=j+1)
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sub #() sub (); // #() for code coverage in verilog.y
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endgenerate
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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