forked from github/verilator
eaf09ba0e7
In order to avoid unexpected breakage on multi-driven variables, we resolve in DFG construction by using only the first driver encountered. Also issues the MULTIDRIVEN error for these signals.
15 lines
1.0 KiB
Plaintext
15 lines
1.0 KiB
Plaintext
%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:16:15: Signal unoptimizable: Circular combinational logic: 't.x'
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16 | wire [2:0] x;
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| ^
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... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest
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... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
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t/t_unoptflat_simple_2.v:16:15: Example path: t.x
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t/t_unoptflat_simple_2.v:13:10: Example path: ASSIGNW
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t/t_unoptflat_simple_2.v:16:15: Example path: t.x
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... Widest variables candidate to splitting:
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t/t_unoptflat_simple_2.v:16:15: t.x, width 3, circular fanout 1, can split_var
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... Candidates with the highest fanout:
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t/t_unoptflat_simple_2.v:16:15: t.x, width 3, circular fanout 1, can split_var
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... Suggest add /*verilator split_var*/ to appropriate variables above.
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%Error: Exiting due to
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