forked from github/verilator
599d23697d
This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
12 lines
777 B
Plaintext
12 lines
777 B
Plaintext
%Warning-UNOPTFLAT: t/t_unopt_combo.v:23:25: Signal unoptimizable: Circular combinational logic: 't.b'
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23 | wire [31:0] b;
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... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest
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... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
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t/t_unopt_combo.v:23:25: Example path: t.b
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t/t_unopt_combo.v:124:4: Example path: ALWAYS
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t/t_unopt_combo.v:24:25: Example path: t.c
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t/t_unopt_combo.v:81:4: Example path: ALWAYS
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t/t_unopt_combo.v:23:25: Example path: t.b
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%Error: Exiting due to
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