forked from github/verilator
27 lines
717 B
Systemverilog
27 lines
717 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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wire [3:0] a = 4'b11z1;
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logic b = 1'bz === a[1];
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logic c = 1'bz === a[2];
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logic d = 2'bzz === 2'(a[1]);
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logic e = 2'b0z === 2'(a[1]);
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always begin
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if (b && !c && !d && e) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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$write("Error: b = %b, c = %b, d = %b, e = %b ", b, c, d, e);
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$write("expected: b = 1, c = 0, d = 0, e = 1\n");
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$stop;
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end
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end
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endmodule
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