forked from github/verilator
25 lines
421 B
Systemverilog
25 lines
421 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2010 by Lane Brooks.
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// SPDX-License-Identifier: CC0-1.0
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module t (clk);
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input clk;
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wire A;
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pullup p1(A);
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child child(/*AUTOINST*/
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// Inouts
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.A (A));
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endmodule
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module child(inout A);
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pulldown p2(A);
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endmodule
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