forked from github/verilator
71 lines
1.8 KiB
Systemverilog
71 lines
1.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2014 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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reg [63:0] crc;
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reg [63:0] sum;
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parameter NPAD = 4;
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tri pad [NPAD-1:0]; // Array
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wire [NPAD-1:0] data0 = crc[0 +: 4];
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wire [NPAD-1:0] data1 = crc[8 +: 4];
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wire [NPAD-1:0] en = crc[16 +: 4];
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for (genvar g=0; g<NPAD; ++g) begin : gpad
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Pad pad1 (.pad(pad[g]),
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.ena(en[g]),
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.data(data1[g]));
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Pad pad0 (.pad(pad[g]),
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.ena(!en[g]),
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.data(data0[g]));
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end
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= {60'h0, pad[3], pad[2], pad[1], pad[0]}
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^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'he09fe6f2dfd7a302
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Pad
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(inout pad,
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input ena,
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input data);
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assign pad = ena ? data : 1'bz;
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endmodule
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