forked from github/verilator
47 lines
1.3 KiB
Perl
Executable File
47 lines
1.3 KiB
Perl
Executable File
#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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# Test tracing with two models instanced
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scenarios(vlt_all => 1);
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top_filename("t_trace_two_a.v");
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compile(
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make_main => 0,
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verilator_make_gmake => 0,
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top_filename => 't_trace_two_b.v',
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vm_prefix => 'Vt_trace_two_b',
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verilator_flags2 => ['-trace'],
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);
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run(
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logfile => "$Self->{obj_dir}/make_first_ALL.log",
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cmd => ["make", "-C", "$Self->{obj_dir}", "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"]
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);
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compile(
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make_main => 0,
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top_filename => 't_trace_two_a.v',
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make_flags => 'CPPFLAGS_ADD=-DTEST_HDR_TRACE=1',
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verilator_flags2 => ['-exe', '-trace', "$Self->{t_dir}/t_trace_two_cc.cpp"],
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);
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execute(
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check_finished => 1,
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);
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if ($Self->{vlt_all}) {
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file_grep("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x);
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vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename});
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}
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ok(1);
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1;
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