forked from github/verilator
38 lines
808 B
Systemverilog
38 lines
808 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014 by Jonathon Donaldson.
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// SPDX-License-Identifier: CC0-1.0
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package my_funcs;
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function automatic int simple_func (input int value);
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begin
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simple_func = value;
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end
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endfunction
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endpackage
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package my_module_types;
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import my_funcs::*;
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localparam MY_PARAM = 3;
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localparam MY_PARAM2 /*verilator public*/ = simple_func(12);
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endpackage
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module t
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import my_module_types::*;
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(
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input i_clk,
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input [MY_PARAM-1:0] i_d,
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output logic [MY_PARAM-1:0] o_q
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);
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always_ff @(posedge i_clk)
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o_q <= i_d;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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