forked from github/verilator
1825 lines
15 KiB
Plaintext
1825 lines
15 KiB
Plaintext
$date
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Wed Feb 23 10:00:37 2022
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$end
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$version
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fstWriter
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$end
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$timescale
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1ps
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$end
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$scope module top $end
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$scope module t $end
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$var wire 1 ! clk $end
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$var int 32 " cyc [31:0] $end
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$var logic 1 # rstn $end
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$var real_parameter 64 $ fst_gparam_real $end
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$var real_parameter 64 % fst_lparam_real $end
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$var real 64 $ fst_real $end
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$var integer 32 & fst_integer [31:0] $end
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$var bit 1 ' fst_bit $end
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$var logic 1 ( fst_logic $end
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$var int 32 ) fst_int [31:0] $end
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$var shortint 16 * fst_shortint [15:0] $end
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$var longint 64 + fst_longint [63:0] $end
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$var byte 8 , fst_byte [7:0] $end
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$var parameter 32 - fst_parameter [31:0] $end
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$var parameter 32 . fst_lparam [31:0] $end
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$var supply0 1 / fst_supply0 $end
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$var supply1 1 0 fst_supply1 $end
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$var tri0 1 1 fst_tri0 $end
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$var tri1 1 2 fst_tri1 $end
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$var tri 1 3 fst_tri $end
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$var wire 1 4 fst_wire $end
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$var logic 5 5 state [4:0] $end
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$scope module test $end
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$var wire 1 ! clk $end
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$var wire 1 # rstn $end
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$var wire 5 5 state [4:0] $end
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$var logic 5 6 state_w [4:0] $end
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$var logic 5 7 state_array[0] [4:0] $end
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$var logic 5 8 state_array[1] [4:0] $end
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$var logic 5 9 state_array[2] [4:0] $end
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$scope module unnamedblk1 $end
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$var int 32 : i [31:0] $end
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$upscope $end
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$scope module unnamedblk2 $end
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$var int 32 ; i [31:0] $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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b00000000000000000000000000000000 ;
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b00000000000000000000000000000000 :
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0/
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b00000000000000000000000111001000 .
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b00000000000000000000000001111011 -
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b00000000 ,
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b0000000000000000000000000000000000000000000000000000000000000000 +
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b0000000000000000 *
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b00000000000000000000000000000000 )
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0(
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0'
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b00000000000000000000000000000000 &
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r4.56 %
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r1.23 $
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0#
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b00000000000000000000000000000000 "
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0!
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$end
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1#
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b00000000000000000000000000000010 ;
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b00000000000000000000000000010011 "
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#813
|
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#814
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#815
|
|
0!
|
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#816
|
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#817
|
|
#818
|
|
#819
|
|
#820
|
|
1!
|
|
b01110 8
|
|
b00000000000000000000000001010010 "
|
|
b00111 9
|
|
b10111 6
|
|
b11100 7
|
|
b11100 5
|
|
#821
|
|
#822
|
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#824
|
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|
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0!
|
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#826
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#827
|
|
#828
|
|
#829
|
|
#830
|
|
1!
|
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b01110 5
|
|
b01110 7
|
|
b11111 6
|
|
b10111 9
|
|
b00000000000000000000000001010011 "
|
|
b00111 8
|
|
#831
|
|
#832
|
|
#833
|
|
#834
|
|
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|
|
0!
|
|
#836
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|
#837
|
|
#838
|
|
#839
|
|
#840
|
|
1!
|
|
b10111 8
|
|
b00000000000000000000000001010100 "
|
|
b11111 9
|
|
b11011 6
|
|
b00111 7
|
|
b00111 5
|
|
#841
|
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|
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|
#844
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|
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|
|
0!
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|
#846
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|
#847
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#848
|
|
#849
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|
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1!
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b10111 5
|
|
b10111 7
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|
b11001 6
|
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b11011 9
|
|
b00000000000000000000000001010101 "
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|
b11111 8
|
|
#851
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|
#852
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|
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|
#854
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|
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|
0!
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|
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|
#857
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|
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|
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|
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|
1!
|
|
b11011 8
|
|
b00000000000000000000000001010110 "
|
|
b11001 9
|
|
b11000 6
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b11111 7
|
|
b11111 5
|
|
#861
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|
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|
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|
#864
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|
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|
0!
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|
#866
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|
#867
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|
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|
#869
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|
#870
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|
1!
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b11011 5
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|
b11011 7
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b01100 6
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b11000 9
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|
b00000000000000000000000001010111 "
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|
b11001 8
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|
#871
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#872
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|
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|
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|
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|
0!
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|
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|
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|
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|
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|
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|
1!
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|
b11000 8
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|
b00000000000000000000000001011000 "
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|
b01100 9
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b00110 6
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b11001 7
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b11001 5
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|
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|
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|
0!
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|
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|
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|
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|
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|
1!
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b11000 5
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b11000 7
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|
b00011 6
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|
b00110 9
|
|
b00000000000000000000000001011001 "
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|
b01100 8
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|
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|
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|
0!
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|
#896
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|
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|
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|
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|
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|
1!
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b00110 8
|
|
b00000000000000000000000001011010 "
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|
b00011 9
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b10101 6
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b01100 7
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b01100 5
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|
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|
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|
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|
0!
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#906
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|
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|
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|
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|
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1!
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b00110 5
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b00110 7
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|
b00000000000000000000000001011011 "
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b00011 8
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|
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|
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|
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|
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|
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b10101 8
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|
b00000000000000000000000001011100 "
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b01111 6
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b00011 7
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b00011 5
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|
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b11110 8
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|
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|
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|
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|
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|
#936
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|
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|
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|
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b01111 8
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b00000000000000000000000001011110 "
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b11110 5
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|
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|
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|
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|
#946
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|
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|
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|
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b01111 5
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b01111 7
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b00000000000000000000000001011111 "
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|
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|
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1!
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b11101 8
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|
b00000000000000000000000001100000 "
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|
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|
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|
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|
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|
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|
#966
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|
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|
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|
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|
b00000000000000000000000001100001 "
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|
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|
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|
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|
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|
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|
#976
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|
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|
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|
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|
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b01101 8
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|
b00000000000000000000000001100010 "
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b01001 6
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|
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|
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|
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|
#986
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|
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|
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b01101 5
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b01101 7
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b10000 6
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b01001 9
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|
b00000000000000000000000001100011 "
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|
b10010 8
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|
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#996
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1!
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b01001 8
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|
b00000000000000000000000001100100 "
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|
b10000 9
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b01000 6
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b10010 7
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|
b10010 5
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|
#1001
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#1003
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