forked from github/verilator
43 lines
798 B
Systemverilog
43 lines
798 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cyc;
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sub1 #(10) sub1a (.*);
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sub1 #(20) sub1b (.*);
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module sub1 #(parameter int ADD)
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(input int cyc);
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wire int value = cyc + ADD;
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sub2 #(ADD + 1) sub2a(.*);
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sub2 #(ADD + 2) sub2b(.*);
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sub2 #(ADD + 3) sub2c(.*);
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endmodule
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module sub2 #(parameter int ADD)
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(input int cyc);
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wire int value = cyc + ADD;
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endmodule
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