forked from github/verilator
59 lines
428 B
Plaintext
59 lines
428 B
Plaintext
$date
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Wed Feb 23 00:00:18 2022
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$end
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$version
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fstWriter
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$end
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$timescale
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1ps
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$end
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$scope module top $end
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$var wire 1 ! clk $end
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$scope module t $end
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$var wire 1 ! clk $end
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$var logic 3 " cyc [2:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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b000 "
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0!
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$end
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#10
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1!
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b001 "
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#15
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0!
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#20
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1!
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b010 "
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#25
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0!
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#30
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1!
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b011 "
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#35
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0!
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#40
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1!
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b100 "
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#45
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0!
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#50
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1!
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b101 "
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#55
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0!
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#60
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1!
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b110 "
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#65
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0!
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#70
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1!
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b111 "
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#75
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0!
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