forked from github/verilator
85 lines
2.6 KiB
Systemverilog
85 lines
2.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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event event1;
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event event2;
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event event3;
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initial begin
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fork
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begin /*empty*/ end
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#8 $write("[%0t] fork..join process 1\n", $time);
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#4 $write("[%0t] fork..join process 2\n", $time);
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#2 $write("[%0t] fork..join process 3\n", $time);
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$write("[%0t] fork..join process 4\n", $time);
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begin : fork_in_fork #16
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$write("[%0t] fork in fork starts\n", $time);
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fork
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#16 $write("[%0t] fork..join process 5\n", $time);
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#8 $write("[%0t] fork..join process 6\n", $time);
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#4 $write("[%0t] fork..join process 7\n", $time);
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$write("[%0t] fork..join process 8\n", $time);
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join
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$write("[%0t] fork..join in fork ends\n", $time);
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end
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join
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#32 $write("[%0t] main process\n", $time);
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fork
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begin
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@event1;
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$write("fork..join_any process 1\n");
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->event1;
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end
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$write("fork..join_any process 2\n");
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join_any
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$write("back in main process\n");
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#1 ->event1;
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#1 fork
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#2 $write("fork..join_any process 1\n");
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begin
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@event1;
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$write("fork..join_any process 2\n");
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->event1;
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end
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join_any
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$write("back in main process\n");
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#1 ->event1;
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@event1;
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// Order of triggering:
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// p1->event2 ==> p2->event3 ==> p3->event3 ==> p2->event2 ==> p1->event3 ==> p3->event1
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fork
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begin
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#1 $write("fork..join_none process 1\n");
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->event2;
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@event2 $write("fork..join_none process 1 again\n");
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#1 ->event3;
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end
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begin
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@event2 $write("fork..join_none process 2\n");
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#1 ->event3;
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@event3 $write("fork..join_none process 2 again\n");
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#1 ->event2;
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end
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begin
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@event3 $write("fork..join_none process 3\n");
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#1 ->event3;
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@event3 $write("fork..join_none process 3 again\n");
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->event1;
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end
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join_none
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$write("in main process\n");
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@event1;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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initial #100 $stop; // timeout
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// Test optimized-out fork statements:
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reg a;
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initial fork a = 1; join
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endmodule
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