forked from github/verilator
32 lines
760 B
Systemverilog
32 lines
760 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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// bug3781
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module t;
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logic clk;
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logic [7:0] data;
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logic [3:0] ptr;
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logic [7:0] mem[16];
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initial begin
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clk = 1'b0;
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fork forever #5 clk = ~clk; join_none
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ptr = '0;
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#10 data = 1;
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#10 if (mem[ptr] != data) $stop;
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#10 data = 2;
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#10 if (mem[ptr] != data) $stop;
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#10 data = 3;
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#10 if (mem[ptr] != data) $stop;
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#10 $write("*-* All Finished *-*\n");
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$finish;
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end
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always @(posedge clk) begin
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mem[ptr] <= #1 data;
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end
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endmodule
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