forked from github/verilator
27 lines
728 B
Systemverilog
27 lines
728 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under The Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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module t;
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timeunit 1ns;
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timeprecision 1ps;
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initial begin
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`checkd($timeunit, -9);
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`checkd($timeunit(), -9);
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`checkd($timeunit(t), -9);
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`checkd($timeprecision, -12);
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`checkd($timeprecision(), -12);
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`checkd($timeprecision(t), -12);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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