verilator/test_regress/t/t_sys_readmem_bad_end2.mem
2021-12-21 19:55:04 -05:00

14 lines
384 B
Plaintext

// DESCRIPTION: Verilator: Verilog Test data file
//
// Copyright 2006 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
10
11
@2
01
// Missing additional data