forked from github/verilator
43 lines
1.2 KiB
Systemverilog
43 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define STRINGIFY(x) `"x`"
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cyc;
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reg [5:0] assoc_c[int];
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reg [95:0] assoc_w[int];
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always_ff @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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assoc_c[300] <= 10; // See if clearing must happen first
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// Also checks no BLKANDNBLK due to readmem/writemem
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end
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else if (cyc == 2) begin
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$readmemb("t/t_sys_readmem_b.mem", assoc_c);
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$display("assoc_c=%p", assoc_c);
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$writememh({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_writemem_c_b.mem"}, assoc_c);
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end
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else if (cyc == 3) begin
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$readmemb("t/t_sys_readmem_b.mem", assoc_w);
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// Not conditional with TEST_VERBOSE as found bug with wide display
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$display("assoc_w=%p", assoc_w);
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$writememh({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_writemem_w_h.mem"}, assoc_w);
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end
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else if (cyc == 4) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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