forked from github/verilator
61 lines
1.8 KiB
Systemverilog
61 lines
1.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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module t;
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`define TRIES 100
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bit [6:0] b5a; // We use larger than [4:0] so make sure we truncate
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bit [6:0] b5b; // We use larger than [4:0] so make sure we truncate
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bit [6:0] b7c;
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bit [6:0] b7d;
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bit [59:0] b60c;
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bit [89:0] b90c;
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bit [6:0] max_b5a;
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bit [6:0] max_b5b;
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bit [6:0] max_b7c;
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bit [6:0] max_b7d;
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bit [59:0] max_b60c;
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bit [89:0] max_b90c;
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initial begin
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for (int i = 0; i < `TRIES; ++i) begin
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// verilator lint_off WIDTH
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// Optimize away extracts
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b5a = {$random}[4:0];
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b5b = {$random}[14:10];
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// Optimize away concats
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b7c = {$random, $random, $random, $random, $random, $random, $random};
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b7d = {{{$random}[0]}, {{$random}[0]}, {{$random}[0]}, {{$random}[0]}, {{$random}[0]}};
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b60c = {$random, $random, $random, $random, $random, $random, $random};
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b90c = {$random, $random, $random, $random, $random, $random, $random};
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// verilator lint_on WIDTH
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max_b5a = max_b5a | b5a;
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max_b5b = max_b5b | b5b;
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max_b7c = max_b7c | b7c;
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max_b7d = max_b7d | b7d;
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max_b60c = max_b60c | b60c;
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max_b90c = max_b90c | b90c;
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end
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`checkh(max_b5a, 7'h1f);
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`checkh(max_b5b, 7'h1f);
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`checkh(max_b7c, 7'h7f);
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`checkh(max_b7d, 7'h1f);
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`checkh(max_b60c, ~ 60'h0);
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`checkh(max_b90c, ~ 90'h0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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