forked from github/verilator
90 lines
3.1 KiB
Systemverilog
90 lines
3.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define STRINGIFY(x) `"x`"
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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//======================================================================
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module t;
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integer file;
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integer r_i;
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byte r_upb[20:10];
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byte r_dnb[20:10];
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reg [13:0] r_ups[20:10];
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reg [13:0] r_dns[10:20];
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reg [30:0] r_upi[20:10];
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reg [30:0] r_dni[10:20];
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reg [61:0] r_upq[20:10];
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reg [61:0] r_dnq[10:20];
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reg [71:0] r_upw[20:10];
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reg [71:0] r_dnw[10:20];
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task clear;
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// Initialize memories to zero,
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// avoid differences between 2-state and 4-state.
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r_i = ~0;
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foreach (r_upb[i]) r_upb[i] = ~0;
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foreach (r_dnb[i]) r_dnb[i] = ~0;
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foreach (r_ups[i]) r_ups[i] = ~0;
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foreach (r_dns[i]) r_dns[i] = ~0;
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foreach (r_upi[i]) r_upi[i] = ~0;
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foreach (r_dni[i]) r_dni[i] = ~0;
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foreach (r_upq[i]) r_upq[i] = ~0;
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foreach (r_dnq[i]) r_dnq[i] = ~0;
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foreach (r_upw[i]) r_upw[i] = ~0;
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foreach (r_dnw[i]) r_dnw[i] = ~0;
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// Open file
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$fclose(file);
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file = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_fread.mem"}, "r");
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if ($feof(file)) $stop;
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endtask
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task dump;
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$write("Dump:");
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$write("\n r_i:"); $write(" %x",r_i);
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$write("\n r_upb:"); foreach (r_upb[i]) $write(" %x", r_upb[i]);
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$write("\n r_dnb:"); foreach (r_dnb[i]) $write(" %x", r_dnb[i]);
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$write("\n r_ups:"); foreach (r_ups[i]) $write(" %x", r_ups[i]);
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$write("\n r_dns:"); foreach (r_dns[i]) $write(" %x", r_dns[i]);
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$write("\n r_upi:"); foreach (r_upi[i]) $write(" %x", r_upi[i]);
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$write("\n r_dni:"); foreach (r_dni[i]) $write(" %x", r_dni[i]);
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$write("\n r_upq:"); foreach (r_upq[i]) $write(" %x", r_upq[i]);
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$write("\n r_dnq:"); foreach (r_dnq[i]) $write(" %x", r_dnq[i]);
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$write("\n r_upw:"); foreach (r_upw[i]) $write(" %x", r_upw[i]);
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$write("\n r_dnw:"); foreach (r_dnw[i]) $write(" %x", r_dnw[i]);
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$write("\n\n");
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endtask
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integer code;
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initial begin
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clear;
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code = $fread(r_i, file); `checkd(code, 4);
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code = $fread(r_upb, file); `checkd(code, 11);
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code = $fread(r_dnb, file); `checkd(code, 11);
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code = $fread(r_ups, file); `checkd(code, 22);
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code = $fread(r_dns, file); `checkd(code, 22);
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code = $fread(r_upi, file); `checkd(code, 44);
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code = $fread(r_dni, file); `checkd(code, 44);
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code = $fread(r_upq, file); `checkd(code, 88);
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code = $fread(r_dnq, file); `checkd(code, 88);
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code = $fread(r_upw, file); `checkd(code, 99);
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code = $fread(r_dnw, file); `checkd(code, 99);
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dump;
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clear;
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code = $fread(r_upb, file, 15); `checkd(code, 6);
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// Bug where fread in if() broke.
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if ($fread(r_ups, file, 15, 2) != 4) $stop;
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dump;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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