forked from github/verilator
24 lines
471 B
Systemverilog
24 lines
471 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module x;
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typedef struct {
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int fst, snd;
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} uselessA_t;
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typedef struct {
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bit [3:0] n;
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uselessA_t b;
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} uselessB_t;
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uselessA_t useless;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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