forked from github/verilator
37 lines
861 B
Systemverilog
37 lines
861 B
Systemverilog
// DESCRIPTION: Verilator:
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// Test an error where a shift amount was out of bounds and the compiler treats the
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// value as undefined (Issue #803)
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014 by Jeff Bush.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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struct packed {
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logic flag;
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logic [130:0] data;
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} foo[1];
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integer cyc = 0;
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// Test loop
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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foo[0].data <= 0;
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foo[0].flag <= !foo[0].flag;
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if (cyc==10) begin
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if (foo[0].data != 0) begin
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$display("bad data value %x", foo[0].data);
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$stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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