forked from github/verilator
130 lines
3.4 KiB
Systemverilog
130 lines
3.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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//Several simulators don't support this.
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//typedef struct pack2; // Forward declaration
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typedef struct packed { // [3:0]
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bit b3;
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bit b2;
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bit b1;
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bit b0;
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} b4_t;
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typedef struct packed { // [3:0]
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b4_t x1;
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b4_t x0;
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} b4x2_t;
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typedef union q4_t; // Forward
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typedef union packed { // [3:0]
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bit [3:0] quad0;
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b4_t quad1;
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} q4_t;
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typedef struct packed { // [5:0]
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bit msb;
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q4_t four;
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bit lsb;
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} pack2_t;
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typedef union packed { // [5:0]
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pack2_t pack2;
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bit [6:1] pvec;
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// Vector not allowed in packed structure, per spec:
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// bit vec[6];
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// bit vec2d[2][3];
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} pack3_t;
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const b4_t b4_const_a = '{1'b1, 1'b0, 1'b0, 1'b1};
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// Cast to a pattern - note bits are tagged out of order
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const b4_t b4_const_b = b4_t'{ b1 : 1'b0, b0 : 1'b1, b3 : 1'b1, b2 : 1'b0 };
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wire b4_t b4_wire;
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assign b4_wire = '{1'b1, 1'b0, 1'b1, 1'b0};
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pack2_t arr[2];
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`ifdef T_STRUCT_INIT_BAD
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const b4_t b4_const_c = '{b1: 1'b1, b1: 1'b0, b0:1'b0, b2: 1'b1, b3: 1'b1};
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`endif
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initial begin
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pack3_t tsu;
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tsu = 6'b110110;
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// 543210
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if (tsu!=6'b110110) $stop;
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if (tsu[5:4]!=2'b11) $stop;
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if (tsu[5:4] == tsu[1:0]) $stop; // Not a good extraction test if LSB subtraction doesn't matter
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if (tsu.pvec!=6'b110110) $stop;
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if (tsu.pvec[6:5]!=2'b11) $stop;
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if (tsu.pack2[5:1] != 5'b11011) $stop;
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if (tsu.pack2.msb != 1'b1) $stop;
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if (tsu.pack2.lsb != 1'b0) $stop;
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if (tsu.pack2.four.quad0 != 4'b1011) $stop;
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if (tsu.pack2.four.quad1.b0 != 1'b1) $stop;
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if (tsu.pack2.four.quad1.b1 != 1'b1) $stop;
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if (tsu.pack2.four.quad1.b2 != 1'b0) $stop;
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if (tsu.pack2.four.quad1.b3 != 1'b1) $stop;
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//
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tsu = 1'b0 ? '0 : '{pvec: 6'b101011};
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if (tsu!=6'b101011) $stop;
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//
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arr[0] = 6'b101010;
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arr[1] = 6'b010101;
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if (arr[0].four !== 4'b0101) $stop;
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if (arr[1].four !== 4'b1010) $stop;
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//
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// Initialization
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begin
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b4_t q = '{1'b1, 1'b1, 1'b0, 1'b0};
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if (q != 4'b1100) $stop;
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end
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begin
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b4_t q = '{3{1'b1}, 1'b0};
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if (q != 4'b1110) $stop;
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end
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begin
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b4_t q = '{4{1'b1}}; // Repeats the {}
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if (q != 4'b1111) $stop;
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end
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begin
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b4x2_t m = '{4'b1001, '{1'b1, 1'b0, 1'b1, 1'b1}};
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if (m != 8'b10011011) $stop;
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end
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begin
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b4_t q = '{default:1'b1};
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if (q != 4'b1111) $stop;
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end
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begin
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b4_t q = '{b0:1'b1, b2:1'b1, b3:1'b1, b1:1'b0};
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if (q != 4'b1101) $stop;
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end
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begin
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b4_t q = '{b2:1'b0, default:1'b1};
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if (q != 4'b1011) $stop;
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end
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if (b4_const_a != 4'b1001) $stop;
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if (b4_const_b != 4'b1001) $stop;
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if (b4_wire != 4'b1010) $stop;
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if (pat(4'b1100, 4'b1100)) $stop;
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if (pat('{1'b1, 1'b0, 1'b1, 1'b1}, 4'b1011)) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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function pat(b4_t in, logic [3:0] cmp);
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if (in !== cmp) $stop;
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pat = 1'b0;
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endfunction
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endmodule
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