forked from github/verilator
107 lines
2.9 KiB
Systemverilog
107 lines
2.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=\"%s\" exp=\"%s\"\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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string str0;
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string str1;
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string str2;
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typedef bit [31:0] bit_t;
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typedef logic [31:0] logic_t;
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typedef bit [55:0] quad_t;
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typedef bit [87:0] wide_t;
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bit_t bdata[3];
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bit_t ldata[3];
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quad_t qdata[3];
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wide_t wdata[3];
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initial begin
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str0 = "sm";
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str1 = "medium";
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str2 = "veryverylongwilltruncate";
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bdata[0] = bit_t'(str0);
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bdata[1] = bit_t'(str1);
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bdata[2] = bit_t'(str2);
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`checks(bdata[0], "sm");
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`checks(bdata[1], "dium");
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`checks(bdata[2], "cate");
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if (bdata[0] != 32'h0000736d) $stop;
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if (bdata[1] != 32'h6469756d) $stop;
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ldata[0] = logic_t'(str0);
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ldata[1] = logic_t'(str1);
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ldata[2] = logic_t'(str2);
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`checks(ldata[0], "sm");
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`checks(ldata[1], "dium");
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`checks(ldata[2], "cate");
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qdata[0] = quad_t'(str0);
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qdata[1] = quad_t'(str1);
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qdata[2] = quad_t'(str2);
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`checks(qdata[0], "sm");
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`checks(qdata[1], "medium");
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`checks(qdata[2], "runcate");
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wdata[0] = wide_t'(str0);
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wdata[1] = wide_t'(str1);
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wdata[2] = wide_t'(str2);
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`checks(wdata[0], "sm");
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`checks(wdata[1], "medium");
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`checks(wdata[2], "illtruncate");
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end
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// Test loop
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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str0 = "z";
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str1 = "zmedi";
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str2 = "ziggylonglonglongtruncate";
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end
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else if (cyc == 2) begin
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bdata[0] = bit_t'(str0);
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bdata[1] = bit_t'(str1);
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bdata[2] = bit_t'(str2);
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ldata[0] = logic_t'(str0);
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ldata[1] = logic_t'(str1);
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ldata[2] = logic_t'(str2);
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qdata[0] = quad_t'(str0);
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qdata[1] = quad_t'(str1);
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qdata[2] = quad_t'(str2);
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wdata[0] = wide_t'(str0);
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wdata[1] = wide_t'(str1);
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wdata[2] = wide_t'(str2);
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end
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else if (cyc == 3) begin
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`checks(bdata[0], "z");
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`checks(bdata[1], "medi");
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`checks(bdata[2], "cate");
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`checks(ldata[0], "z");
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`checks(ldata[1], "medi");
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`checks(ldata[2], "cate");
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`checks(qdata[0], "z");
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`checks(qdata[1], "zmedi");
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`checks(qdata[2], "runcate");
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`checks(wdata[0], "z");
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`checks(wdata[1], "zmedi");
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`checks(wdata[2], "ongtruncate");
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end
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//
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else if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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