forked from github/verilator
30 lines
827 B
Systemverilog
30 lines
827 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t(/*AUTOARG*/);
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// Unpacked byte from string IEEE 1800-2017 5.9
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byte bh[3:0] = "hi2";
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byte bl[0:3] = "lo2";
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initial begin
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`checkh(bh[0], "2");
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`checkh(bh[1], "i");
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`checkh(bh[2], "h");
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`checkh(bh[3], 0);
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`checkh(bl[0], 0);
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`checkh(bl[1], "l");
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`checkh(bl[2], "o");
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`checkh(bl[3], "2");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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