forked from github/verilator
14 lines
319 B
Systemverilog
14 lines
319 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2022 by Antmicro Ltd.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
module t (/*AUTOARG*/);
|
|
wire (strong1, strong1) a = 1;
|
|
initial begin
|
|
$stop;
|
|
end
|
|
|
|
endmodule
|