forked from github/verilator
49 lines
1.2 KiB
Systemverilog
49 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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interface inter (input logic cond, output wire a);
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parameter W;
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// Example:
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wire (weak0, weak1) [W-1:0] b = '1;
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assign (strong0, strong1) b = cond ? 'b0 : 'bz;
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assign a = b[10];
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endinterface
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module t (clk1, clk2);
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input wire clk1;
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input wire clk2;
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wire (weak0, weak1) a = 0;
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assign (supply0, supply1) a = 1'bz;
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assign (pull0, pull1) a = 1;
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wire [2:0] b;
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assign b = 3'b101;
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assign (supply0, supply1) b = 3'b01z;
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wire c;
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and (weak0, weak1) (c, clk1, clk2);
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assign (strong0, strong1) c = 'z;
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assign (pull0, pull1) c = 0;
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wire d;
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inter #(.W(32)) i(.cond(1'b1), .a(d));
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always begin
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if (a === 1 && b === 3'b011 && c === 0 && d === 0) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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$write("Error: a = %b, b = %b, c = %b, d = %b", a, b, c, d);
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$write("expected: a = %b, b = %b, c = %b, d = %b\n", clk1, 3'b011, 0, 0);
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$stop;
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end
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end
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endmodule
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