forked from github/verilator
3abb65d732
Declare every AstNode children and variables as AstNodeExpr where we statically know this is the appropriate sub-type.
15 lines
344 B
Systemverilog
15 lines
344 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic [31:0] packed_data_32;
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byte byte_in[4];
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initial packed_data_32 = {<<$random{byte_in}};
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endmodule
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