forked from github/verilator
43 lines
803 B
Systemverilog
43 lines
803 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2021 by Adrien Le Masle.
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// SPDX-License-Identifier: CC0-1.0
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//module t;
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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logic [63:0] din;
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logic [63:0] dout;
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always_comb begin
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dout = {<<8{din}};
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end
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always @(posedge clk) begin
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if (cyc != 0) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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din <= 64'h1122334455667788;
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end
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if (cyc == 2) begin
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if (dout != 64'h8877665544332211) $stop;
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end
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if (cyc == 3) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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