forked from github/verilator
101 lines
2.5 KiB
Systemverilog
101 lines
2.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2014 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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reg [63:0] crc;
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reg [63:0] sum;
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/*AUTOWIRE*/
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generate
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for (genvar width=1; width<=16; width++) begin
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for (genvar amt=1; amt<=width; amt++) begin
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Test #(.WIDTH(width),
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.AMT(amt))
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test (.ins(crc[width-1:0]));
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end
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end
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endgenerate
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x\n",
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$time, cyc, crc);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h0
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test (/*AUTOARG*/
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// Inputs
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ins
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);
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parameter WIDTH = 1;
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parameter AMT = 1;
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input [WIDTH-1:0] ins;
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reg [WIDTH-1:0] got;
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reg [WIDTH-1:0] expec;
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int istart;
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int bitn;
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int ostart;
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always @* begin
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got = { << AMT {ins}};
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// Note always starts with right-most bit
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expec = 0;
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for (istart=0; istart<WIDTH; istart+=AMT) begin
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ostart = WIDTH - AMT - istart;
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if (ostart<0) ostart = 0;
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for (bitn=0; bitn<AMT; bitn++) begin
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if ((istart+bitn) < WIDTH
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&& (istart+bitn) >= 0
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&& (ostart+bitn) < WIDTH
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&& (ostart+bitn) >= 0) begin
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expec[ostart+bitn] = ins[istart+bitn];
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end
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end
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end
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`ifdef TEST_VERBOSE
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$write("[%0t] exp %0d'b%b got %0d'b%b = { << %0d { %0d'b%b }}\n", $time, WIDTH, expec, WIDTH, got, AMT, WIDTH, ins);
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`endif
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`checkh(got, expec);
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end
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endmodule
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