forked from github/verilator
68e1b473e2
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
12 lines
258 B
Systemverilog
12 lines
258 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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package std;
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endpackage
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module t;
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endmodule
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