forked from github/verilator
18 lines
370 B
Systemverilog
18 lines
370 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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package foo;
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`ifdef TEST_DECLARE_STD
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class std;
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static int bar;
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endclass
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`endif
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endpackage
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module t;
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int baz = foo::std::bar;
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endmodule
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