forked from github/verilator
f3b10df454
* add tests to reproduce #3177. Any random test circuits can be added to t_split_var_4.v later because it uses CRC to check the result while t_split_var_0.v has just barrel shifters. * Fix #3177. Don't merge assign statements if a variable is marked split_var.
25 lines
773 B
Perl
Executable File
25 lines
773 B
Perl
Executable File
#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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verilator_flags2 => ['--stats', '-DENABLE_SPLIT_VAR=1'],
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);
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execute(
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check_finished => 1,
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);
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file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/i, 1);
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file_grep($Self->{stats}, qr/SplitVar,\s+Split unpacked arrays\s+(\d+)/i, 0);
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ok(1);
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1;
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