forked from github/verilator
28 lines
735 B
Systemverilog
28 lines
735 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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bit a [5:0];
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bit b [5:0];
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initial begin
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a = '{1, 1, 1, 0, 0, 0};
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b = '{0, 0, 0, 1, 1, 1};
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$display(":assert: ('%b%b%b_%b%b%b' == '111_000')",
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a[5], a[4], a[3], a[2], a[1], a[0]);
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$display(":assert: ('%b%b%b_%b%b%b' == '000_111')",
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b[5], b[4], b[3], b[2], b[1], b[0]);
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if ((a[5:3] == b[2:0]) != 1'b1) $stop;
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if ((a[5:3] != b[2:0]) != 1'b0) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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