forked from github/verilator
62 lines
1.3 KiB
Systemverilog
62 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Methods defined by IEEE:
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// class semaphore;
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// function new(int keyCount = 0);
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// function void put(int keyCount = 1);
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// task get(int keyCount = 1);
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// function int try_get(int keyCount = 1);
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// endclass
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`ifndef SEMAPHORE_T
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`define SEMAPHORE_T semaphore
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`endif
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// verilator lint_off DECLFILENAME
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module t(/*AUTOARG*/);
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// From UVM:
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`SEMAPHORE_T s;
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`SEMAPHORE_T s2;
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initial begin
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s = new(1);
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if (s.try_get() == 0) $stop;
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if (s.try_get() != 0) $stop;
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s = new;
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if (s.try_get() != 0) $stop;
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s.put();
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s.get();
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s.put(2);
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s.get(2);
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s.put(2);
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if (s.try_get(2) <= 0) $stop;
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fork
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begin
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#10; // So later then get() starts below
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s.put(1);
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s.put(1);
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end
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begin
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if (s.try_get(1) != 0) $stop;
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s.get(); // Blocks until put
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s.get();
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end
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join
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s2 = new;
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if (s2.try_get() != 0) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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