forked from github/verilator
56 lines
1.5 KiB
Systemverilog
56 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2004 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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reg [255:0] a;
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reg [255:0] q;
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reg [63:0] qq;
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integer i;
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always @* begin
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for (i=0; i<256; i=i+1) begin
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q[255-i] = a[i];
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end
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q[27:16] = 12'hfed;
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for (i=0; i<64; i=i+1) begin
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qq[63-i] = a[i];
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end
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qq[27:16] = 12'hfed;
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end
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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`ifdef TEST_VERBOSE
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$write("%x/%x %x\n", q, qq, a);
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`endif
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if (cyc==1) begin
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a = 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
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end
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if (cyc==2) begin
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a = 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
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if (q != 256'h64fe7e285bcf892eca128d426ed707a20eebc824d5d9127bacbc21362fed1cb7) $stop;
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if (qq != 64'h64fe7e285fed892e) $stop;
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end
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if (cyc==3) begin
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if (q != 256'h1da9cf939c0712504b5bdbbbbfbb6c47c316bd471362641958a7fabcffede870) $stop;
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if (qq != 64'h1da9cf939fed1250) $stop;
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end
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if (cyc==4) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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