forked from github/verilator
12 lines
692 B
Plaintext
12 lines
692 B
Plaintext
%Warning-LITENDIAN: t/t_select_bad_msb.v:12:8: Big bit endian vector: left < right of bit range: [0:22]
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: ... In instance t
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12 | reg [0:22] backwd;
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| ^
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... For warning description see https://verilator.org/warn/LITENDIAN?v=latest
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... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.
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%Warning-SELRANGE: t/t_select_bad_msb.v:16:16: [1:4] Range extract has backward bit ordering, perhaps you wanted [4:1]
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: ... In instance t
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16 | sel2 = mi[1:4];
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| ^
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%Error: Exiting due to
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