forked from github/verilator
599d23697d
This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
48 lines
1.1 KiB
Systemverilog
48 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2022 by Geza Lore. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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`ifdef VERILATOR
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// The '$c1(1)' is there to prevent inlining of the signal by V3Gate
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`define IMPURE_ONE $c(1);
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`else
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// Use standard $random (chaces of getting 2 consecutive zeroes is zero).
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`define IMPURE_ONE |($random | $random);
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`endif
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module top(
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clk
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);
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input clk;
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reg clk_half = 0;
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reg [31:0] cyc = 0;
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reg [31:0] a, b, c;
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always @(posedge clk) begin
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$display("tick %d: a: %d, b: %d, c: %d", cyc, a, b, c);
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// Check invariant
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if (a !== cyc + 1) $stop;
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if (b !== cyc + 2) $stop;
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if (c !== cyc + 2) $stop;
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// End of test
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if (cyc == 100) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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cyc <= cyc + 1;
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end
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always @(clk) a = cyc + `IMPURE_ONE;
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always @(a) b = a + `IMPURE_ONE;
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assign c = a + `IMPURE_ONE;
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endmodule
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