forked from github/verilator
22 lines
428 B
Systemverilog
22 lines
428 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int a = 0;
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function int f(output int a);
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a = 1;
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return a;
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endfunction
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assert property (@(posedge clk) f(a) >= 0);
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endmodule
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