forked from github/verilator
48 lines
1012 B
Systemverilog
48 lines
1012 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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typedef enum int {
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RANDOMIZED = 20
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} enumed_t;
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class Cls;
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int pre;
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rand enumed_t r;
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int post;
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function void pre_randomize;
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if (pre != 0) $stop;
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$display("%d", r);
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if (r != enumed_t'(0)) $stop;
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if (post != 0) $stop;
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pre = 10;
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endfunction
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function void post_randomize;
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if (pre != 10) $stop;
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if (r != RANDOMIZED) $stop;
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if (post != 0) $stop;
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post = 30;
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endfunction
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endclass
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module t (/*AUTOARG*/);
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initial begin
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Cls c;
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int rand_result;
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c = new;
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rand_result = c.randomize();
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if (rand_result != 1) $stop;
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if (c.pre != 10) $stop;
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if (c.r != RANDOMIZED) $stop;
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if (c.post != 30) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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