forked from github/verilator
22 lines
642 B
Systemverilog
22 lines
642 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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typedef struct packed { int x, y; } point;
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initial begin
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point points_q[$];
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point points_qv[$];
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points_q.push_back(point'{1, 2});
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// `index` should be treated as normal member select,
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// but the member is not present in the struct
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points_qv = points_q.find_first(a) with (a.x.index == 0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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