forked from github/verilator
19 lines
375 B
Systemverilog
19 lines
375 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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initial begin
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int i;
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i = {} + 1;
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i = {};
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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